Reconciling Sharing and Spatial Locality Using Adjustable Block Size Coherent Caches

Several studies have shown that the performance of coherent caches depends on the relationship between the cache block size and the granularity of sharing and locality exhibited by the program. Large cache blocks exploit processor and spatial locality, but may cause unnecessary cache invalidations due to false sharing. Small cache blocks can reduce the number of cache invalidations, but increase the number of bus or network transactions required to load data into the cache. To reduce the performance impact of a mismatch between the cache block size and the sharing pattern exhibited by a given application, we propose to adjust the amount of data stored in a cache line dynamically according to recent reference patterns. In this scheme, cache blocks are split across cache lines when false sharing occurs, and merged back into a single cache line to exploit spatial locality. Results of simulations of a scalable multiprocessor indicate that, over a range of applications, an adjustable block size cache performs better than every xed block size alternative. Moreover, for a given program, the adjustable block size cache is comparable in performance to the best xed block size cache for that program. We conclude that adjusting the block size in response to reference behavior can signi cantly improve performance, especially when there is variability in the granularity of sharing exhibited by applications. This research was supported by the National Science Foundation under grant CDA-8822724.